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esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 1/49 revision history revision 0.1 (15 jan. 2002) - original revision 0.2 (19 nov. 2002) -changed ordering information & dc/ac characteristics revision 0.1 revision 0.2 m13s128168a - 5t m13s128168a - 6t m13s128168a - 6t m13s128168a - 7.5ab revision 0.3 (8 aug. 2003) -change idd6 from 3ma to 5ma. revision 0.4 (27 aug. 2003) -change ordering information & dc / ac characteristics. revision 1.0 (21 oct. 2003) -modify twtr from 2tck to 1tck. revision 1.1 (10 nov. 2003) -correct some refresh interval that is not revised. -correct some cas lantency that is not revised. revision 1.2 (12 jan. 2004) -correct idd1; idd4r and idd4w test condition. -correct trcd; trp unit -add tccd spec. -add tdal spec. revision 1.3 (12 mar. 2004) -add cas latency=2; 2.5 revision 1.4 (23 jun. 2005) -add pb-free to ordering information -modify idd0 and idd1 spec -modify some ac timing un it from tck to ns. revision 1.5 (29 may. 2006) -delete cl2 ; cl2.5 -modify trefi -delete non-pb-free form ordering information revision 1.6 (3 jan. 2007) -add cl2.5 revision 1.7 (12 apr. 2007) -add bga package revision 1.8 (01 jun. 2007) -delete cl 2.5
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 2/49 ddr sdram 2m x 16 bit x 4 banks double data rate sdram features z jedec standard z internal pipelined double-data-rate architecture, two data access per clock cycle z bi-directional data strobe (dqs) z on-chip dll z differential clock inputs (clk and clk ) z dll aligns dq and dqs transition with clk transition z quad bank operation z cas latency : 3 z burst type : sequential and interleave z burst length : 2, 4, 8 z all inputs except data & dm are sampled at the rising edge of the system clock(clk) z data i/o transitions on both edges of data strobe (dqs) z dqs is edge-aligned with data for reads; center-aligned with data for write z data mask (dm) for write masking only z v dd = 2.375v ~ 2.75v, v ddq = 2.375v ~ 2.75v z auto & self refresh z 15.6us refresh interval (64ms refresh period, 4k cycle) z sstl-2 i/o interface z 66pin tsopii package ordering information : product no. max freq vdd package comments m13s128168a -5tg 200mhz pb-free m13s128168a -6tg 166mhz 2.5v tsopii pb-free m13s128168a -5bg 200mhz pb-free m13s128168a -6bg 166mhz 2.5v bga pb-free
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 3/49 control logic functional block diagram pin arrangement bank a command decoder bank d latch circuit bank b bank c dm dq mode register & extended mode register column address buffer & refresh counter row address buffer & refresh counter row decoder sense amplifier column decoder data control circuit input & output buffer address clock generator clk clk cke cs ras cas we dll dqs clk, clk dqs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 pin tsop(ii) (400mil x 875mil) (0.65 mm pin pitch) v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq dq 7 nc v ddq ldqs nc v dd nc ldm we cas ras cs nc ba 0 ba 1 a 10 /ap a 0 a 1 a 2 a 3 v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq dq 8 nc v ssq udq s nc v ref v ss udm cl k cl k cke nc nc a 11 a 9 a 8 a 7 a 6 a 5 a 4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 x16 x16
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 4/49 60 ball bga v ssq dq14 dq12 dq10 dq8 v ref a b c d e f g h j k l m dq15 v ddq v ssq v ddq v ssq v ss clk nc a11 a8 a6 a4 v ss dq13 dq11 dq9 udqs udm clk cke a9 a7 a5 v ss v ddq dq1 dq3 dq5 dq7 nc v dd dq2 dq4 dq6 ldqs ldm we ras ba1 a0 a2 v dd dq0 v ssq v ddq v ssq v ddq v dd cas cs ba0 a10/ap a1 a3 123 789 pin description (m13s128168a) pin name function pin name function a0~a11, ba0,ba1 address inputs - row address a0~a11 - column address a0~a8 a10/ap : auto precharge ba0, ba1 : bank selects (4 banks) ldm, udm dm is an input mask signal for write data. ldm corresponds to the data on dq0~dq7; udm correspond to the data on dq8~dq15. dq0~dq15 data-in/data-out clk, clk clock input ras row address strobe cke clock enable cas column address strobe cs chip select we write enable v ddq supply voltage for gdq v ss ground v ssq ground for dq v dd power v ref reference voltage for sstl-2 ldqs, udqs bi-directional data strobe. ldqs corresponds to the data on dq0~dq7; udqs correspond to the data on dq8~dq15. nc no connection
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 5/49 absolute maximum rating parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v voltage on v ddq supply relative to v ss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d tbd w short circuit current i os 50 ma note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restrict ed to recommend operation condition. exposure to higher than recommended voltage for exten ded periods of time could affect device reliability. dc operation condition & specifications dc operation condition recommended operating conditions (voltage reference to v ss = 0v, t a = 0 to 70 c ) parameter symbol min max unit note supply voltage v dd 2.375 2.75 v i/o supply voltage v ddq 2.375 2.75 v i/o reference voltage v ref 0.49*v ddq 0.51*v ddq v 1 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 2 input logic high voltage v ih (dc) v ref + 0.15 v ddq + 0.3 v input logic low voltage v il (dc) -0.3 v ref - 0.15 v input voltage level, clk and clk inputs v in (dc) -0.3 v ddq + 0.3 v input differential voltage, clk and clk inputs v id (dc) 0.36 v ddq + 0.6 v input leakage current i i -5 5 a 3 output leakage current i oz -5 5 a output high current (normal strengt h driver) (v out =v ddq -0.373v, min v ref , min v tt ) i oh -16.8 ma output low current (normal strength driver) (v out = 0.373v) i ol +16.8 ma output high current (weak strength driver) (v out =v ddq -0.763v, min v ref , min v tt ) i oh -9 ma output low current (weak strength driver) (v out = 0.763v) i ol +9 ma notes 1. v ref is expected to be equal to 0.5* v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 2. v tt is not applied directly to the device. v tt is system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 3. v id is the magnitude of the difference between t he input level on clk and the input level on clk .
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 6/49 dc specifications version parameter symbol test condition -5 -6 unit note operation current (one bank active) idd0 t rc = t rc (min) t ck = t ck (min) active ? precharge 170 145 ma operation current (one bank active) idd1 burst length = 2 t rc = t rc (min), cl= 2.5 i out = 0ma, active-read- precharge 175 150 ma precharge power-down standby current idd2p cke v il (max), t ck = t ck (min), all banks idle 40 40 ma idle standby current idd2n cke v ih (min), cs v ih (min), t ck = t ck (min) 115 95 ma active power-down standby current idd3p all banks act, cke v il (max), t ck = t ck (min) 50 45 ma active standby current idd3n one bank; active-precharge, t rc = t ras (max), t ck = t ck (min) 120 110 ma operation current (read) idd4r burst length = 2, cl= 2.5 , t ck = t ck (min), i out = 0ma 245 215 ma operation current (write) idd4w burst length = 2, cl= 2.5 , t ck = t ck (min) 240 200 ma auto refresh current idd5 t rc t rfc (min) 270 250 ma self refresh current idd6 cke 0.2v 5 5 ma 1 note 1. enable on-chip refresh and address counters. ac operation conditions & timing specification ac operation conditions parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih (ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il (ac) v ref - 0.31 v input different voltage, clk and clk inputs v id (ac) 0.7 v ddq +0.6 v 1 input crossing point voltage, clk and clk inputs v ix (ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 note1. v id is the magnitude of the difference betwe en the input level on clk and the input on clk . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must tra ck variations in the dc level of the same. input / output capacitance (v dd = 2.375v~2.75v, v ddq =2.375v~2.75v, t a = 25 c , f = 1mhz) parameter symbol min max unit input capacitance (a0~a11, ba0~ba1, cke, cs , ras , cas , we ) c in1 2.5 3.5 pf input capacitance (clk, clk ) c in2 2.5 3.5 pf data & dqs input/output capacitance c out 4.0 5.5 pf input capacitance (dm) c in3 4.0 5.5 pf
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 7/49 ac operating test conditions parameter value unit input reference voltage for clock (v ref ) 0.5*v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate 1.0 v/ns input levels (v ih /v il ) v ref +0.31/v ref -0.31 v input timing measurement reference level v ref v output timing reference level v tt v ac timing parameter & specifications (v dd = 2.375v~2.75v, v ddq =2.375v~2.75v, t a =0 c to 70 c )(note) -5 -6 parameter symbol min max min max clock period cl3 t ck 5.0 10 6.0 10 ns access time from clk/ clk t ac -0.7 +0.7 -0.7 +0.7 ns clk high-level width t ch 0.45 0.55 0.45 0.55 t ck clk low-level width t cl 0.45 0.55 0.45 0.55 t ck data strobe edge to clock edge t dqsck -0.6 +0.6 -0.6 +0.6 ns clock to first rising edge of dqs delay t dqss 0.75 1.25 0.75 1.25 t ck data-in and dm setup time (to dqs) t ds 0.45 - 0.45 - ns data-in and dm hold time (to dqs) t dh 0.45 - 0.45 - ns dq and dm input pulse width (for each input) t dipw 1.75 - 1.75 - ns input setup time (fast slew rate) t is 0.75 - 0.75 - ns input hold time (fast slew rate) t ih 0.75 - 0.75 - ns input setup time (slow slew rate) t is 0.8 - 0.8 - ns input hold time (slow slew rate) t ih 0.8 - 0.8 - ns control and address input pulse width t ipw 2.2 - 2.2 - ns dqs input high pulse width t dqsh 0.4 0.6 0.4 0.6 t ck dqs input low pulse width t dqsl 0.4 0.6 0.4 0.6 t ck dqs falling edge to clk rising-setup time t dss 0.2 - 0.2 - t ck dqs falling edge from clk rising-hold time t dsh 0.2 - 0.2 - t ck data strobe edge to output data edge t dqsq - 0.45 - 0.45 ns data-out high-impedance window from clk/ clk t hz -0.7 +0.7 -0.7 +0.7 ns data-out low-impedance window from clk/ clk t lz -0.7 +0.7 -0.7 +0.7 ns
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 8/49 ac timing parameter & specifications-continued -5 -6 parameter symbol min max min max half clock period t hp t cl min or t ch min - t cl min or t ch min - ns dq-dqs output hold time t qh t hp -0.45 - t hp -0.5 - ns active to precharge command t ras 40 120kns 42 120kns ns row cycle time t rc 60 - 60 - ns auto refresh row cycle time t rfc 70 - 72 - ns active to read,write delay t rcd 18 - 18 - ns precharge command period t rp 18 - 18 - ns active to read with autoprecharge command t rap 18 120k 18 120k ns active bank a to active bank b command t rrd 10 - 12 - ns write recovery time t wr 2 - 2 - t ck write data in to read command delay t wtr 1 - 1 - t ck col. address to col. address delay t ccd 1 - 1 - t ck average periodic refresh interval t refi - 15.6 - 15.6 us write preamble t wpre 0.25 - 0.25 - t ck write postamble t wpst 0.4 0.6 0.4 0.6 t ck dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck clock to dqs write preamble setup time t wpres 0 - 0 - ns load mode register / extended mode register cycle time t mrd 2 - 1 - t ck exit self refresh to read command t xsrd 200 - 200 - t ck exit self refresh to non-read command t xsnr 75 - 75 - ns autoprecharge write recovery+precharge time t dal (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) t ck
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 9/49 command truth table command cken-1 cken cs ras cas we dm ba0,1 a10/ap a11, a9~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x xx 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge enable h x l h l h x v h column address 4 auto precharge disable l 4 write & column address auto precharge enable h x l h l l x v h column address 4,6 burst stop h x l h h l x x 7 bank selection v l precharge all banks h x l l h l x x h x 5 h x x x entry h l l v v v x active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dm h x v x 8 h x x x no operation command h x l h h h xx (v = valid, x = don?t care, h = logic high, l = logic low) 1. op code: operand code. a0~a11 & ba0~ba1 : program keys. (@emrs/mrs) 2. emrs/mrs can be issued only at all banks precharge state. a new command can be issued 1 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by ?auto?.. auto/self refresh can be issued onl y at all banks precharge state. 4. ba0~ba1 : bank select addresses. if both ba0 and ba1 are ?low? at read, write, row active and precharge, bank a is selected. if ba0 is ?high? and ba1 is ?low? at read, writ e, row active and precharge, bank b is selected. if ba0 is ?low? and ba1 is ?high? at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are ?high? at read, write, row active and precharge, bank d is selected. 5. if a10/ap is ?high? at row precharge, ba0 and ba1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command ca n be issued after the end of burst. new row active of the associated bank can be issued at t rp after end of burst. 7. burst stop command is valid at every burst length. 8. dm sampling at the rising and falling edges of the dqs and da ta-in are masked at the both edges (write dm latency is 0).
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 10/49 basic functionality power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke at a low state (all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as v tt & v ref ). 2. start clock and maintain stable condition for a minimun of 200us. 3. the minimun of 200us after stable power and clock (clk, clk ), apply nop & take cke high. 4. issue precharge commands fo r all banks of the device. *1 5. issue emrs to enable dll. (to issue ?dll enable? comma nd, provide ?low? to a0, ?high? to ba0 and ?low? to all of the rest address pins, a1~a11 and ba1) *1 6. issue a mode register set command for ?dll reset?. the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide ?high? to a8 and ?low? to ba0) *2 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command with low to a8 to initialize device operation. *1 every ?dll enable? command resets dll. therefore sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll. *2 sequence of 6 & 7 is regardless of the order. clk clk command 0 1 2345678910111213141516171819 t rp precharge all banks emrs mrs dll reset t rp precharge all banks 1st auto re fres h t rfc 2nd auto re fre sh t rfc mode re gi ste r s e t any command min. 200 cycle power up & initialization sequence
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 11/49 mode register definition mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dl l reset and various vendor specific options to make ddr sdram useful for variety of different applications. the default valu e of the register is not def ined, therefore the mode register must be written after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on cs , ras , cas , we and ba0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the mode register). the state of address pins a0~a11 in the same cycle as cs , ras , cas , we and ba0 going low is written in the mode register. two clock cycles are requested to complete the write operation in the m ode register. the mode register c ontents can be changed using the same command and clock cycle requirements during operation as lo ng as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a0~a2, addressing mode uses a3, cas latency (read latency from column address) uses a4~a6. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. refer to the table for specific c odes for various burst length, addressing modes and cas latencies. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 0 0 rfu dll tm cas latency bt burst length mode register a8 dll reset a7 mode a3 burst type 0 no 0 normal 0 sequential 1 yes 1 test 1 interleave burst length cas latency latency a6 a5 a4 latency a2 a1 a0 sequential interleave ba1 ba0 operating mode 0 0 0 reserve 0 0 0 reserve reserve 0 0 mrs cycle 0 0 1 reserve 0 0 1 2 2 0 1 emrs cycle 0 1 1 3 0 1 0 4 4 1 0 1 reserve 0 1 1 8 8 1 1 0 reserve 1 0 0 reserve reserve 1 1 1 reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 12/49 burst address ordering for burst length burst length starting address (a2, a1,a0) sequential mode interleave mode xx0 0, 1 0, 1 2 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 4 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 dll enable / disable the dll must be enabled for normal operation. dll enable is required during power-up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation (upon exitin g self refresh mode, the dll is enable automatically). any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. m13s1281 68a also support a weak drive strength option, intended for lighter load and/or point-to-point environments. mode register set *1 : mrs can be issued only at all banks precharge state. *2 : minimum t rp is required to issue mrs command. 01 234 5678 command t ck precharge all banks mode register set an y command t rp *2 *1 clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 13/49 extended mode register set (emrs) the extended mode register stores the data enabling or disabling dll. the default value of the extended mode register is not defined, therefore the extended mo de register must be written after power up for enabling or disabling dll. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the extend ed mode register). the state of address pins a0~a11 and ba1 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. the m ode register contents can be changed using the same command and clock cycle requirement s during operation as long as al l banks are in the idle state. a0 is used for dll enable or disable. ?high? on ba0 is used fo r emrs. all the other address pins except a0 and ba0 must be set to low for proper emrs operation. refe r to the table for specific codes. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 rfu : must be set ?0? d.i.c dll output driver strength control a0 dll enable 0 normal 0 enable 1 weak 1 disable ba1 ba0 operaing mode 0 0 mrs cycle 0 1 emrs cycle *qfc is not used; don?t care.
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 14/49 precharge the precharge command is used to precharge or close a bank that has activat ed. the precharge command is issued when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank se lect addresses (ba0, ba1) are used to define which bank is precharged when the command is in itiated. for write cycle, t wr (min.) must be satisfied until the precharge command can be issued. after t rp from the precharge, an active command to the same bank can be initiated. burst selection for precharge by bank address bits a10/ap ba1 ba0 precharge 0 0 0 bank a only 0 0 1 bank b only 0 1 0 bank c only 0 1 1 bank d only 1 x x all banks nop & device deselect the device should be deselected by deactivating the cs signal. in this mode ddr sdram should ignore all the control inputs. the ddr sdrams are put in nop mode when cs is active and by deactivating ras , cas and we . for both deselect and nop the device should finish the current operation when this command is issued.
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 15/49 row active the bank activation command is issued by holding cas and we high with cs and ras low at the rising edge of the clock (clk). the ddr sdram has four indepe ndent banks, so two bank select addres ses (ba0, ba1) are required. the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time (t rcd min). once a bank has been activated, it must be precharged before a nother bank activation command can be applied to the same bank. the minimum time interval between interleaved bank activation comma nd (bank a to bank b and vice versa) is the bank to bank delay time (t rrd min). bank activation command cycle ( cas latency = 3) read bank this command is used after the row activate command to init iate the burst read of data. t he read command is initiated by activating cs , cas , and deasserting we at the same clock sampling (rising) edge as described in the command truth table. the length of the burst and the cas lat ency time will be determined by the values programmed during the mrs command. write bank this command is used after the row activate command to initiate the burst write of data. the write command is initiated by activating cs , cas , and we at the same clock sampling (rising) edge as de scribe in the command trut h table. the length of the burst will be determined by the val ues programmed during the mrs command. address 01 2 command bank a row addr. bank a col. addr. bank a row. addr. bank b row addr. bank a activate nop write a with auto precharge bank b activate nop bank a activate ras-cas delay ( t rcd ) ras-ras delay ( t rrd ) row cycle time ( t rc ) : don't care clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 16/49 essential functionality for ddr sdram burst read operation burst read operation in ddr sdram is in the same manner as the current sdram such that the burst read command is issued by asserting cs and cas low while holding ras and we high at the rising edge of the clock (clk) after t rcd from the bank activation. the address inputs de termine the starting address for the burst, the mode register sets type of burst (sequential or interleave) and burst length (2, 4, 8). the first output data is available after the cas latency from the read command, and the consecutive data are presented on the falling and rising edge of data strobe (dqs) adopted by ddr sdram until the burst length is completed. 01 234 5678 co mmand read a nop no p nop no p nop nop nop no p clk clk cas latency=3 dqs dq' s dout0 do ut1 do ut2 dout3
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 17/49 burst write operation the burst write command is issued by having cs , cas and we low while holding ras high at the rising edge of the clock (clk). the address inputs determine the starting column addr ess. there is no write latency relative to dqs required for b urst write cycle. the first data of a burst writ e cycle must be applied on the dq pins t ds (data-in setup time) prior to data strobe edge enabled after t dqss from the rising edge of the clock (c lk) that the write command is issued. the remaining data inputs must be supplied on each subsequent falling and rising edge of data str obe until the burst length is comp leted. when the burst has been finished, any additional data supplied to the dq pins will be ignored. 01 234 5678 command dqs dq's nop write nop nop nop nop nop nop t dqss t wpst din0 din1 din2 din3 t wpres clk clk t dsh t dss nop
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 18/49 read interrupted by a read a burst read can be interrupted before completion of the burst by new read command of any bank. when the previous burst is interrupted, the remaining addresses are ove rridden by the new address with the full burst length. the data from the first read command continues to appe ar on the outputs until the cas latency from the interrupting read command is satisfied. at this point the data from the interrupting read command appears. read to read interval is minimum 1 clock. read interrupted by a write & burst stop to interrupt a burst read with a write command, burst stop command must be asserted to avoid data contention on the i/o bus by placing the dq?s(output driv ers) in a high impedance state. to insure t he dq?s are tri-stated one cycle before the beginning the write operation, burt stop command mu st be applied at least ru(cl) clocks ru means round up to the nearest integer before the write command. t ccd cas latency=3 01 234 5678 command dqs dq's read a nop nop nop nop nop nop nop dout a 0 read b dout a 1 dout b 2 dout b 3 dout b 0 dout b 1 clk clk cas latency=3 01 234 5678 command dqs dq's read nop write nop nop nop nop nop dout 0 burst stop din 0 dout 1 din 1 din 2 din 3 clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 19/49 read interrupted by a precharge a burst read operation can be interrupted by precharge of the sa me bank. the minimum 1 clock is required for the read to precharge intervals. a precharge command to out put disable latency is equivalent to the cas latency. when a burst read command is issued to a ddr sdram, a prec harge command may be issued to the same bank before the read burst is complete. the following functionality determines when a precharge command may be given during a read burst and when a new bank activate command may be issued to the same bank. 1. for the earliest possible precharge command without interr upting a read burst, the precharge command may be given on the rising clock edge which is cl clock cycles befor e the end of the read burst where cl is the cas latency. a new bank activate command may be issued to the same bank after t rp (ras precharge time). 2. when a precharge command interrupts a read burst operation, the precharge command may be given on the rising clock edge which is cl clock cycles before the last data fr om the interrupted read burst where cl is the cas latency. once the last data word has been output, the output buffers are tristated. a new bank activate command may be issued to the same bank after t rp . 3. for a read with autoprecharge command, a new bank acti vate command may be issued to the same bank after t rp where t rp begins on the rising clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. during read with autoprecharge, the initia tion of the internal precharge occurs at the same time as the earliest possible external precharge command would initiate a precharge operati on without interrupting the read burst as described in 1 above. 4. for all cases above, t rp is an analog delay that needs to be converted into clock cycles. the number of clock cycles between a precharge command and a new bank activate command to the same bank equals t rp / t ck (where t ck is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. in all cases, a precharge operati on cannot be initiated unless t ras (min) [minimum bank activate to precharge time] has been satisfied. this includes read with autoprecharge commands where t ras (min) must still be satisfied such that a read with autoprecharge command has the same timing as a read comm and followed by the earliest possible precharge command which does not interrupt the burst. cas latency=3 01 234 5678 command dqs dq's read nop nop nop nop nop nop dout 0 precharge dout 1 1t ck nop dout 2 dout 3 dout 4 dout 5 interrupted by precharge dout 6 dout 7 clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 20/49 write interrupted by a write a burst write can be interrupted before completion of the burst by a new write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. when the prev ious burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satis fied. the following functionality establishes how a write command may interrupt a read burst. 1. for write commands interrupting a read burst, a read burst, a burst terminate command is requi red to stop the read burst and tristate the dq bus prior to valid input write data. on ce the burst terminate command has been issued, the minimum delay to a write command = ru(cl) [cl is the cas latency and ru means round up to the nearest integer]. 2. it is illegal for a write command to in terrupt a read with autoprecharge command. 01 234 5678 command dqs dq's nop no p nop no p nop nop din a 0 write a din a 1 di n b 0 din b 1 di n b 2 din b 3 1t ck nop write b clk clk t ccd
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 21/49 write interrupted by a read & dm a burst write can be interrupted by a read command of any bank . the dq?s must be in the hi gh impedance state at least one clock cycle before the interrupting read data appear on the output s to avoid data contention. w hen the read command is register ed, any residual data from the burst write cycle must be ma sked by dm. the delay from the last data to read command (t wtr ) is required to avoid the data contention dram inside. data that ar e presented on the dq pins before the read command is initiated will actually be written to the memory. read command interrupting wr ite can not be issued at the next clock edge of that of wri te command. the following functionality established how a read command may in terrupt a write burst and which input data is not written into the memory. 1. for read commands interrupting a write burst, the minimum wr ite to read command delay is 2 clock cycles. the case where the write to read delay is 1 clock cycle is disallowed. 2. for read commands interrupting a write burst, the dm pin must be used to mask t he input data words which immediately precede the interrupting read operation and the input data word which immediat ely follows the interrupting read operation. 3. for all cases of a read interrupting a write, the dq and dqs buses must be releas ed by the driving chip (i.e., the memory controller) in time to allow the buses to turn arou nd before the sdram drives t hem during a read operation. 4. if input write data is masked by the read co mmand, the dqs inputs is ignored by the sdram. 5. it is illegal for a read command interrupt a write with autoprecharge command. cas latency=3 01 234 5678 command dqs dq's cas latency=3 dqs dq's nop nop nop nop read nop nop nop t dqssmax din 0 din 1 write t wpres t wtr din 2 din 3 din 4 din 5 din 6 din 7 dout 0 dout 1 t dqssmin din 0 din 1 t wpres t wtr din 2 din 3 din 4 din 5 din 6 din 7 dout 0 dout 1 dm clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 22/49 write interrupted by a precharge & dm a burst write operation can be interrupted before completion of the burst by a precharge of the same bank. random column access is allowed. a write recovery time (t wr ) is required from the last data to pr echarge command. when precharge command is asserted, any residual data from the burst write cycle must be masked by dm. precharge timing for write operations in drams requires enough time to allow ?write recovery? which is the time required by a dram core to properly store a full ?0? or ?1? level before a precharge operation. for ddr sdram, a timing parameter, t wr , is used to indicate the required of time between the last valid write operation and a precharge command to the same bank. the precharge timing for writes is a complex definition since t he write data is sampled by the data strobe and the address is sampled by the input clock. inside the sdram, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain. this makes the definition of when a precha rge operation can be initiated after a writ e very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain. t wr starts on the rising clock edge after the last possible dqs edge that strobed in the last va lid and ends on the rising clock edge that strobes in the precharge command. 01 234 5678 command dqs dq's dqs dq's nop nop nop nop n o p precharge nop t dqssmax dina0 dina1 write a dina2 dina3 dina4 dina5 dina6 dina7 t dqssmin dm write b dinb0 t wr dina0 dina1 dina2 dina3 dina4 dina5 dina6 dina7 dinb0 dinb1 clk clk t wr
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 23/49 1. for the earliest possible precharge command following a write burst without interrupting the burst, the minimum time for wri te recovery is defined by t wr . 2. when a precharge command interrupts a write burst operation, the data mask pin, dq, is used to mask input data during the time between the last valid write data and the rising clock edge in which the precharge command is given. during this time, the dqs input is still required to strobe in the state of dm. the minimum time for write recovery is defined by t wr . 3. for a write with autoprecharge command, a new bank ac tivate command may be issued to the same bank after t wr + t rp where t wr + t rp starts on the falling dqs edge that strobed in the last valid data and ends on the rising clock edge that strobes in the bank activate commands. during write with aut oprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external precharge command without interrupting the write burst as described in 1 above. 4. in all cases, a precharge operation cannot be initiated unless t ras (min) [minimum bank activate to precharge time] has been satisfied. this includes write with autoprecharge commands where t ras (min) must still be satisfied such that a write with autoprecharge command has the same timing as a write command followed by the earliest possible precharge command which does not interrupt the burst. burst stop the burst stop command is initiated by having ras and cas high with cs and we low at the rising edge of the clock (clk). the burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. w hen the burst stop command is issued during a burst read cycle, the pair of data and dqs (data strobe) go to a high impedance stat e after a delay which is equal to the cas latency set in the mode register. the burst stop command, however, is not s upported during a writ e burst operation. 01 234 5678 command read a nop nop nop nop nop nop nop burst stop clk clk cas latency=3 dqs dq's dout 0 dout 1
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 24/49 the burst stop command is a mandatory feature for ddr sdrams. the following functionality is required. 1. the bst command may only be issued on t he rising edge of the input clock, clk. 2. bst is only a valid command during read burst. 3. bst during a write burst is undefined and shall not be used. 4. bst applies to all burst lengths. 5. bst is an undefined command during read with autoprecharge and shall not be used. 6. when terminating a burst read command, the bst command must be issued l bst ( ?bst latency?) clock cycles before the clock edge at which the output buffers are tristated, where l bst equals the cas latency for read operations. 7. when the burst terminates, the dq and dqs pins are tristated. the bst command is not byte controllable and applies to all bits in the dq data word and the (all) dqs pin(s). dm masking the ddr sdram has a data mask function that can be used in conjunction with data write cycle. not read cycle. when the data mask is activated (dm high) during wr ite operation, ddr sdram does not accept the corresponding data. (dm to data-mask latency is zero) dm must be issued at t he rising or falling edge of data strobe. 01 234 5678 command t dqss dqs dq's dm write nop nop nop nop nop nop nop din 0 nop din 1 din 2 din 3 din 4 din 6 din 7 din 5 masked by dm = h clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 25/49 read with auto precharge if a read with auto-precharge command is in itiated, the ddr sdram automatically ente rs the precharge operation bl/2 clock later from a read with auto-precharge command when t ras (min) is satisfied. if not, the start point of precharge operation will be delayed until t ras (min) is satisfied. once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (t rp ) has been satisfied 01234 5678 command ba nk a active nop nop nop nop nop nop nop read a auto pre cha rg e clk clk cas latency=3 dqs dq's dout 0 dout 1 dout 2 dout 3 t rap at burst read / write with auto precharge, cas interrupt of the same bank is illegal.
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 26/49 write with auto precharge if a10 is high when write command is issued, the write with auto-precharge function is perfo rmed. any new command to the same bank should not be issued until the internal precharge is completed. the internal precharge begins after keeping t wr (min). auto refresh & self refresh auto refresh an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock(clk). all banks must be precharged and idle for t rp (min) before the auto refresh command is applied. no control of the external address pins is requires once this cycle has started because of the internal address counter. when the refresh cycle h as completed, all banks will be in the idle state. a delay bet ween the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t rfc (min). a maximum of eight consecutive auto refrsh commands (with trfcmin) can be posted to any given sdram, and the maximum absolute interval between any auto refresh command and the next auto refresh command is 8x15.6 m. 01 234 5678 command dqs dq's bank a active nop nop nop nop nop nop nop dout 0 dout 1 write a auto precharge dout 2 dout 3 *bank can be reactivated at completion of t rp t wr t rp in te r nal p r echa r g e sta r t clk clk command cke = high t rp pre au t o refresh cmd t rfc clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 27/49 self refresh a self refresh command is defines by having cs , ras , cas and cke held low with we high at the rising edge of the clock (clk). once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. during t he self refresh operation, all inpu ts except cke are ignored. the clock is intern ally disabled during self refresh operation to re duce power consumption. the self refresh is exited by supplying st able clock input before returning cke high, asserting deselect or nop command and then asserting cke high for longer than t xsrd for locking of dll. power down power down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding clk, clk and cke. for maximum power savings, the user has the option of disabling the dll prior to enterin g power-down. in that case, the dll mus t be enabled after exiting power-down, and 200 clock cycles mu st occur before a read command can be issued. however, power-down duration is limited by the refresh requirements of t he device, so in most applicati ons, the self-refresh mode is pre ferred over the dll disable power-down mode. in the power-down, c ke low and a stable clock signal mu st be maintained at the inputs of the ddr sdram, and all other input signals are ?don?t care?. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid executable command may be applied one clock cycle later. command cke t xsnr self refresh au to refresh read t xsrd clk clk command cke clk clk valid nop nop valid enter power-down mode no column acess in program t is t is exit power-down mode
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 28/49 functional truth table. current cs ras cas we address command action h x x x x desel nop l h h h x nop nop l h h l ba burst stop illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra active bank active, latch ra l l h l ba, a10 pre / prea nop*4 l l l h x refresh auto-refresh*5 idle l l l l op-code mode-add mrs mode register set*5 h x x x x desel nop l h h h x nop nop l h h l ba burst stop nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto -precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto -precharge l l h h ba, ra active bank active/illegal*2 l l h l ba, a10 pre / prea precharge/precharge all l l l h x refresh illegal row active l l l l op-code mode-add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba burst stop terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a10 write / writea illegal l l h h ba, ra active bank active/illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refresh illegal read l l l l op-code mode-add mrs illegal
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 29/49 current state cs ras cas we address command action h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba burst stop illegal l h l h ba, ca, a10 read/reada terminate burst with dm=high, latch ca, begin read, determine auto-precharge*3 l h l l ba, ca, a10 write/writea terminate burst, latch ca, begin new write, determine auto-precharge*3 l l h h ba, ra active bank active/illegal*2 l l h l ba, a10 pre / prea terminal burst with dm=high, precharge l l l h x refresh illegal write l l l l op-code mode-add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba burst stop illegal l h l h ba, ca, a10 read read*7 l h l l ba, ca, a10 write illegal l l h h ba, ra active bank active/illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refresh illegal read with auto precharge l l l l op-code mode-add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba burst stop illegal l h l h ba, ca, a10 read illegal l h l l ba, ca, a10 write write l l h h ba, ra active bank active/illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refresh illegal write with auto precharge l l l l op-code mode-add mrs illegal
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 30/49 current state cs ras cas we address command action h x x x x desel nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l ba burst stop illegal*2 l h l x ba, ca, a10 read/write illegal*2 l l h h ba, ra active illegal*2 l l h l ba, a10 pre / prea nop*4 (idle after t rp ) l l l h x refresh illegal pre-chargin g l l l l op-code mode-add mrs illegal h x x x x desel nop (row active after t rcd ) l h h h x nop nop (row active after t rcd ) l h h l ba burst stop illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra active illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refresh illegal row activating l l l l op-code mode-add mrs illegal h x x x x desel nop l h h h x nop nop l h h l ba burst stop illegal*2 l h l h ba, ca, a10 read illegal*2 l h l l ba, ca, a10 write write l l h h ba, ra active illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refresh illegal write recovering l l l l op-code mode-add mrs illegal
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 31/49 current state cs ras cas we address command action h x x x x desel nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l ba burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal l l h l ba, a10 pre / prea illegal l l l h x refresh illegal re-freshing l l l l op-code mode-add mrs illegal h x x x x desel nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l ba burst stop illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra active illegal l l h l ba, a10 pre / prea illegal l l l h x refresh illegal mode register setting l l l l op-code mode-add mrs illegal abbreviations : h = high level, l = low level, v = valid, x = don?t care ba = bank address, ra =row address, ca = column address, nop = no operation note : 1. all entries assume that cke wa s high during the preceding clock cy cle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indica ted by ba, depending on the state of the bank. 3. must satisfy bus contention, bus turn around and write recovery requirements. 4. nop to bank precharging or in idle st ate. may precharge bank indicated by ba. 5. illegal of any bank is not idle. 6. same bank?s previous auto precharg will not be performed. but if the bank is different, previous auto precharge will be performed. 7. refer to ?read with auto precharge: for more detailed information. illegal = device operation and / or data integrity ar e not guaranteed.
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 32/49 current state cke n-1 cke n cs ras cas we add action h x x x x x x invalid l h h x x x x exit self-refresh l h l h h h x exit self-refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self-refreshing* 1 l l x x x x x nop (maintain self-refresh) h x x x x x x invalid l h x x x x x exit power down (idle after t pdex ) power down l l x x x x x nop (maintain power down) h h x x x x x refer to function true table h l l l l h x enter self-refresh h l h x x x x exit power down h l l h h h x exit power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal all banks idle*2 l l l x x x x refer to current state = power down h h x x x x x refer to function true table any state other than listed above abbreviations : h = high level, l = low level, v = valid, x = don?t care note : 1. cke low to high transition will re-enable clk, clk and other inputs asynchronously. a minimum setup time must be satisfied before issuing any command other than exit. 2. power-down and self-refresh can be entered only from all bank idle state.
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 33/49 basic timing (setup, hold and access time @ bl=4, cl=3) note 1. t hp is lesser of t cl or t ch clock transition collectively when a bank is active. cke cs ras cas ba0,ba1 addr (a0~an) we dqs dq 01 234 5678910 high dm command a 10 /ap baa bab cb db0 db1 db3 db2 t ck t is t ih t dqsck t rpre t lz t dqsq t dqsck da0 da1 da2 da3 t rpst hi-z hi-z t dqss t wpres t dqsh t dqsl t ds t dh t ds t dh t wpst hi-z hi-z read write clk clk t cl t wpre baa t hp note1 t hz t ac t qh
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 34/49 multi bank interleaving read (@bl=4, cl=3)
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 35/49 multi bank interleaving write (@bl=4)
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 36/49 read with auto precharge (@bl=8) note 1. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of another activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same bank is illegal. cke cs ras cas ba0,ba1 we dqs(cl=3) dq(cl=3) 01 234 5678910 high dm command a 10 /ap addr (a0~an) baa qa4 qa5 qa7 qa6 baa t rp qa0 qa1 qa3 qa2 ac tive read ca auto precharge start note1 clk clk ra ra
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 37/49 write with auto precharge (@bl=8) note 1. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of another activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal.
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 38/49 read interrupted by precharge (@bl=8)
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 39/49 read interrupted by a read (@bl=8, cl=3)
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 40/49 read interrupted by a write & burst stop (@bl=8, cl=3) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command baa qa0 qa1 read qb0 qb5 qb1 qb4 qb3 qb2 qb6 bab cb burst stop write qb7 clk clk a 10 /ap addr (a0~an) ca
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 41/49 write followed by precharge (@bl=4) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command a 10 /ap addr (a0~an) baa baa t wr da0 da1 da3 da2 pre char ge write ca clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 42/49 write interrupted by precharge & dm (@bl=8)
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 43/49 write interrupted by a read (@bl=8, cl=3) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command baa t wtr da0 da1 da3 da2 write read ca clk clk bab cb da5 da4 qb0 qb1 qb3 qb2 qb4 qb5 maskecd by dm a 10 /ap addr (a0~an)
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 44/49 dm function (@bl=8) only for write cke cs ras cas ba0,ba1 we dqs(cl=3) dq(cl=3) 01 234 5678910 high dm command a 10 /ap addr (a0~an) baa qa4 qa5 qa7 qa6 qa0 qa1 qa3 qa2 write ca clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 45/49 power up & initialization sequence cke cs ras cas a8 precharge all bank a7 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 dq precharge all bank ba0 a10/ap we dqs high-z high-z t rp high level is required ba1,a9,a11 a1~a6 a0 address key minimum 200 cycle t rp t rfc t rfc minimum of 2 refresh cycles are required power & clock must be stable for 200us emrs dll enable mrs dll reset 1st auto refresh 2nd auto refresh mode resister set any command : don't care clk clk
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 46/49 mode register set cke cs ras cas addr (a0~an) precharge command all bank dm dq mode register set command any command ba0,ba1 a10/ap t ck we dqs address key high-z high-z t rp clk clk t mrd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 47/49 packing dimensions 66-lead tsop(ii) dram(400mil) symbol dimension in inch dimension in mm min norm max min norm max a 0.047 1.2 a1 0.002 0.004 0.006 0.05 0.1 0.15 a2 0.037 0.039 0. 041 0.95 1 1.05 b 0.009 0.015 0.22 0.38 b1 0.009 0.012 0. 013 0.22 0.3 0.33 c 0.005 0.008 0.12 0.21 c1 0.0047 0.005 0.006 0.12 0.127 0.16 d 0.875 bsc 22.22 bsc zd 0.028 ref 0.71 ref e 0.455 0.463 0.471 11 .56 11.76 11.96 e1 0.400 bsc 10.16 bsc e 0.026 bsc 0.65 bsc l 0.016 0.02 0.024 0.4 0.5 0.6 l1 0.031 ref 0.80 ref 10 15 20 10 15 20 1 10 15 20 10 15 20
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 48/49 packing dimensions 60-ball ddr sdram ( 8x13 mm ) symbol dimension in mm dimension in inch min norm max min norm max a 1.20 0.047 a 1 0.30 0.35 0.40 0.012 0.014 0.016 a 2 0.80 0.031 b 0.40 0.45 0.50 0.016 0.018 0.020 d 7.90 8.00 8.10 0.311 0.315 0.319 e 12.90 13.00 13.10 0.508 0.512 0.516 d 1 6.40 0.252 e 1 11.0 0.433 e 0.80 0.031 e 1 1.00 0.039 controlling dimension : millimeter.
esmt m13s128168a elite semiconductor memory technology inc. publication date : jun. 2007 revision : 1.8 49/49 important notice all rights reserved. no part of this document may be reproduc ed or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the product s or specification in this document without notice. the information contained herein is presen ted only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, copyrights, or ot her intellectual propert y rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. a ny semiconductor devices may have inhere ntly a certain rate of failure. to minimize risks associated with custom er's application, adeq uate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or caus e physical injury or property damage. if products described here are to be used for such kinds of applicat ion, purchaser must do its own quality assurance test ing appropriate to such applications.

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